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[VHDL-FPGA-Verilog] uartvhdl

Description: 一个在FPGA芯片上实现UART功能的vhdl源代码，提供了UART的集成-an FPGA chip to achieve UART function vhdl source code, providing integrated UART
Platform: | Size: 10240 | Author: 王利 | Hits:

[VHDL-FPGA-Verilog] uart0vhdl

Description: vhdl实现fpga和PC机的简单通信(发送),-vhdl achieve fpga and PC simple communication (transmission),
Platform: | Size: 1024 | Author: 刘音 | Hits:

[Software Engineering] aticle

Description: 一篇介绍基于FPGA的UART电路的设计的文章。-introduced a UART-based FPGA circuit design articles.
Platform: | Size: 154624 | Author: zjz | Hits:

[VHDL-FPGA-Verilog] UART_ise7_bak

Description: 用FPGA 实现全双工异步串口（UART），与PC 机通信。1 位起始位；8 位数据位；一个停止位；无校验位；波特率为2400、4800、9600、11520 任选或可变（可用按键控制波特率模式）。-using FPGA full-duplex asynchronous serial port (UART), and PC communication. An initiation; 8 data spaces; One-stop; No Parity; Baud Rate for 2400,4800,9600, 11520 optional or variable (baud rate can be used to control keypad mode).
Platform: | Size: 32768 | Author: lee | Hits:

[Books] Quartus-guide

Description: quartus的教程，是初学者使用FPGA的好老师，介绍了quartus的使用方法，并且有例子-quartus curricula, the use of FPGA beginners is a good teacher. quartus introduced the use, and is an example
Platform: | Size: 1183744 | Author: mh | Hits:

[Embeded-SCM Develop] quartusII

Description: quartusII 中文使用手册，给广大cpld 及 fpga 开发用户使用，谢谢大家的支持。-Chinese quartusII user manual to the general development of CPLD and FPGA users, I would like to thank everyone
Platform: | Size: 2369536 | Author: hrbu | Hits:

[VHDL-FPGA-Verilog] uartsourcecode

Description: uart的FPGA模块，基于VHDL、verilog语言-the FPGA UART modules, based on VHDL, verilog language
Platform: | Size: 293888 | Author: 王辉 | Hits:

[VHDL-FPGA-Verilog] VHDLserial

Description: UART参考设计带缓存用于Xinlix用于FPGA-UART reference design with cache for Xinlix for FPGA
Platform: | Size: 279552 | Author: sd | Hits:

[VHDL-FPGA-Verilog] fftinterface

Description: 电赛一等奖作品：音频信号分析仪的FPGA源码，VHDL编写，Quartus7.1综合，ModelSim6.2g se仿真，应用了opencores.org上的开源FFT IP核，加入了8051总线接口和ram-Xinhua Cup first prize works: audio signal analyzer FPGA source, VHDL prepared, Quartus7.1 integrated, ModelSim6.2g se simulation, application of open source opencores.org on FFT IP core, joined the 8051 bus interface and ram
Platform: | Size: 4933632 | Author: 李星 | Hits:

[VHDL-FPGA-Verilog] uart_vhdl

Description: vhdl的异步串口代码，可以方便以致在不同的FPGA中-asynchronous serial VHDL code, can easily result in different FPGA in
Platform: | Size: 18432 | Author: 李冰 | Hits:

[source in ebook] fpga_uart

Description: 基于FPGA 实现异步串口可以值得参考。-Asynchronous FPGA-based serial port can be worth considering.
Platform: | Size: 10240 | Author: chenwei | Hits:

[Com Port] rec

Description: uart串口通信程序 用VERILOG HDL　编写　可以有效应用于FPGA上-UART serial communication program with VERILOG HDL can be effectively used in the preparation of the FPGA
Platform: | Size: 1024 | Author: 德刚 | Hits:

[VHDL-FPGA-Verilog] Fusion_UART

Description: UART实验Verilog HDL代码，用于FPGA-UART experimental Verilog HDL code for FPGA
Platform: | Size: 3072 | Author: 张猛蛟 | Hits:

[VHDL-FPGA-Verilog] uart

Description:
Platform: | Size: 14336 | Author: 顾向南 | Hits:

[MPI] UART_Download

Description: 此为FPGA上的一个串口通信程序，已经通过仿真测试，完全可行-This is the FPGA a serial communication program has been tested through simulation, entirely feasible
Platform: | Size: 9216 | Author: 王骏 | Hits:

[VHDL-FPGA-Verilog] S7_UART

Description: 利用FPGA实现串口通信，很好的学习资料 尤其是对 verilog不熟的朋友-FPGA realization of the use of serial communications, a very good learning materials especially in the wake of a friend Verilog
Platform: | Size: 468992 | Author: 杜菲 | Hits:

[VHDL-FPGA-Verilog] FPGA-VHDL

Description: FPGA相关硬件仿真程序，编译环境QUARTER Ⅱ。-FPGA hardware simulation program, the compiler environment QUARTER Ⅱ.
Platform: | Size: 493568 | Author: 黄国江 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
Platform: | Size: 1024 | Author: saibei007 | Hits:

[Software Engineering] fpgadesign

Description: FPGA/CPLD数字电路设计经验分享，有助于设计能力提高-FPGA/CPLD digital circuit design experience to share, contribute to the design capacity to improve
Platform: | Size: 837632 | Author: 小武 | Hits:

[VHDL-FPGA-Verilog] fpga_uartrw

Description: FPGA的uart控制器的verilog源程序，在cyclone II EP2C8Q208上调试运行成功-FPGA s UART controller Verilog source code, in cyclone II EP2C8Q208 debugging run successfully
Platform: | Size: 55296 | Author: 蒋斌斌 | Hits:
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